Carry generation means for multiple character adder

ABSTRACT

An addition stage of a binary multiple character adder is receptive to input signals, including operand bits from each of the characters and carry-in bits from previous lower order stages. The outputs include the sum for that stage and carry-out signals to succeeding higher order stages. Means are provided for determining the pattern of the input signals and for generating at least one carry-out signal from another carry-out signal in accordance with the input pattern.

" States Patent Sept. 4, 1973 [54] CARRY GENERATION MEANS FOR 3,586,8456/1971 Komamiya 235/175 X MULTIPLE CHARACTER ADDER 3,566,098 2/1971 Kono235/175 [75] Inventor: 58;] Macey Wright, Cinnaminson, Primary Examinerpefix D. Gruber Assistant Examiner-James F. Gottman [73] Assignee: RCACorporation, Princ t NJ, AttorneyH. Christoffersen, C. V. Olson andSamuel h 22 Filed: May 12, 1972 C0 [21] Appl. No.: 252,589 [57] ABSTRACTAn addition stage of a binary multiple character adder 52 us. (:1.235/175, 235/173 is receptive to input Signals. including operand bits[51] Int. Cl. G061 7/385 from each of the characters and ybits from P[58] Field of Search 235/175, 172, 173, vious lower Order Stages TheOutputs include the Sum 235 1 for that stage and carry-out signals tosucceeding higher order stages. Means are provided for determin- 5 R fren i d ing the pattern of the input signals and for generating UNITEDSTATES PATENTS at least one carry-out signal from another carry-out sig-3,506,817 4/1970 Winder 235/175 x ml m accordance the mput pattern3,535,502 10/1970 Clapper 235/175 X 9 Claims, 3 Drawing Figures cu C1K1-2 a1 (:1 K -2 bi K1-1 PARITY CHECKER b1 Ki-l PAIENTEBSEP 4mm SHEET 10F 2 PAR ITY CHECKER Fig. 3.

PATENTED 35? 41973 sum 2 or 2 m ER N: E N; E E E .U E 6 5. .p s a a N:3x 5 a 3x 5 Ex 5 2x 5 5 5 N 6 Ix a 5 6 5 5 CARRY GENERATION MEANS FORMULTIPLE CHARACTER ADDER BACKGROUND OF THE memos I Multiple characteradders have application in the field of digital computers whenever it isdesired to add multiple sets of ordered or weighted bits together in onepass. For instance, in a double step multiplier, the partial product isformed by adding the multiplicand to th partial product (which isinitial zero) a number of times depending on the multiplier digit. Athree character adder can perform the two necessary additions in oneoperation.

When two binary characters are added, bit by bit, in stages of a twocharacter adder, the presence of two binary 1 s will generate acarry-out signal that is a binary l which must be added together withthe next succeeding higher order bits in the next succeeding higherorder addition stage. Therefore, each stage of a two character addermust have provisions for summing three bits and providing a carry-out tothe next succeeding higher order addition stage. In the addition ofthree characters, bit by bit, in stages of a three character adder, eachstage must accomodate five input bits, comprising three operand bits, alower order carry-in from the next previous lower order stage, and ahigher order carry-in from the second previous lower order stage is atypical addition stage of the multiple character adder. The inputsignals to an addition stage comprise the operand bits for that stageand carry-in bits from previous lower order stages. The carry-in bits 5from previous lower order stages are, of course, the

stage, and must generate the sum of the five bits, a

lower order carry-out to the next succeeding higher order stage, and ahigher order carry-out to the second succeeding higher order stage. Asthe number of characters to be added together increases, the number ofcarry-out signals which must be generated also increases.

The sum of the binary inputs to an addition stage of a multiplecharacter adder may be derived by a parity checker and is well known inthe art. The carry-out signals can be independently derived by any oneof various logic configurations. This invention relates to thegeneration of one carry-out signal from another carryout signal.

SUMMARY OF THE INVENTION An improved multiple character adder in whichthe input signals to an adder stage are examined and at least onecarry-out signal is generated from another carry-out signal in a mannerdependent on the input signal pattern which is present.

BRIEF DESCRIPTION OF THE DIAGRAMS FIG. 1 is the truth table for thebinary addition of bits containing up to fifteen binary 1's.

FIG. 2 is a schematic diagram of an addition stage of a three characteradder using AND or OR gates and embodying the invention.

FIG. 3 is a schematic diagram of an addition stage of a three characteradder using threshold" logic gates and embodying the invention.

DETAILED DESCRIPTION OF THE DRAWING FIG. 1 is the truth table for thebinary addition of groups of bits containing up to 15 binary ls. Thecolumns are labeled Number of Input ls, SJQ K and K the columne labeledNumber of Input ls contains, in increasing order, the number of binaryls that may be present at any one time among the inputs to the i"addition stage of a multiple character adder. The i carry-out bits ofthose stages. S is the binary sum of the inputs to the i" stage. K K andK are the carryout signals which must be generated by the 1"" stage,depending on the number of characters to be added, and are,respectively, the carry-out to the next succeeding higher order stage,the carry-out to the second succeeding higher order stage, and thecarry-out to the third succeeding higher order stage. If two charactersare added, provisions must be made to generate and transmit thecarry-out signals K to the next succeeding higher order stage. If threecharacters are added, provisions must be made to generate and transmitthe carry-out signals K and K to the next two succeeding higher orderstages, respectively. If six characters are added, provisions must bemade to generate and transmit the carry-out signals K K and K to thenext three succeeding higher order stages, respectively. The truth tablein FIG. 1 can be easily verified by adding any number of binary ls up tofifteen and looking at the sum digit, which is the least significant orrightmost digit of the result, the K digit, which is the digit to theleft of the sum digit, the K digit, which is the digit to the left ofthe K digit, and the K digit, which is the digit to the left of the Kdigit.

Certain relationships are present in FIG. I. The sum digit for a stage,8,, is a 1 when the number of input ls is odd and is otherwise a 0.There are certain input patterns for which one carry-out signal is thecomplement of another. For instance, if the number of input l-s is inthe range between 2 and 5, inclusive, or in the range between 10 and 13,inclusive, the carry-out signals K, and K are complements of oneanother, and, for all other numbers of input ls in FIG. 1 they are thesame. The complementary relationship between K and K is indicated bydashed lines S and 5 5. Dashed lines 6a, 6b, and 66 indicate thecomplementary relationship between K.- and K when the number of inputTs'isin tlierange betweenzand 3, inclusive, in the range between 6 and9, inclusive, and in the range between 12 and 13, inclusive. Dashed line7 indicates that carry-out signals K1 and K, are complements in therange of number of input ls between 4 and 11, inclusive. It is to benoted that if the truth table in FIG. 1 were extended for higher numbersof input ls beyond 15, the complementary relationships between carry-outsignals indicated by the dashed lines 5a, Sb, 6a, 6b, 6c, and 7 wouldrepeat every time another carry-out signal was generated. For instance,if it were possible to have 16 input ls, a carryout, K to the fourthsucceeding higher order stage after the present would have to begenerated. At 32 input ls, a carry-out, K to the fifth succeeding higherorder stage after the present would have to be generated. Betweensixteen input ls and 32 input ls the relationships between K K and K isexactly the same as it is between zero input ls and 15 input I s.

The area indicated by dashed line 8 is the truth table for the binaryaddition performed in an addition stage of a three character adder. Aswas just described, the lower order carry-out (carry-out to the nextsucceeding higher order stage), K and the higher order carryout(carry-out to the second succeeding higher order stage), K arecomplements in the range of input ls between 2 and 5, inclusive. Viewedin another way, the lower order carry-out, K is the complement of thehigher order carry-out, K whenever the number of input ls is greaterthan one and is otherwise the same as the higher order carry-out, KAlthough the following description relates to two circuits forgenerating the lower order carry-out from the higher order carryout in athree character adder utilizing this relationship, it should be notedthat the higher order carry-out could be generated from the lower ordercarry-out. lt is evident that the technique of generating one carry-outfrom another carry-out in accordance to what input pattern is present,is generally useful in any multiple character adder.

FIG. 2 is a schematic of the i addition stage of a three character adderusing AND or OR gates. The inputs to the stage are labeled a, b,, 0,, Kand K and are respectfully the three digits from the i order bitpositions of three operand characters a, b, and c, the lower ordercarry-in signal from the next previous lower order stage, and the higherorder carry-in signal from the second previous lower order stage.Herein, for purposes of convenience, the terms signal and digit are usedinterchangeably. The lower order carry-in signal, K is the lower ordercarry-out signal from the next previous lower order stage and the higherorder carry-in signal, K, is the higher order carry-out signal from thesecond previous lower order stage. The outputs are labeled 8,, K and Kand are respectively the sum digit of the 1'' addition stage, the lowerorder carryout digit and the higher order carry-out digit of the i"addition stage.

Parity checker receives the five inputs and produces the sum, 8,, whichis a binary l solely when the number of binary 1 inputs is odd.

AND gates 11 through 15 and OR gate 16 form the logic network togenerate the higher order carry-out signal, K Each of the AND gates 11through 15 receives a different combination of four of the five inputsignals. The output of each AND gate 11 through 15 is connected to aninput terminal of OR gate 16. The output of OR gate 16 is the higherorder carry K AND gates 17 through 26, OR gate 27, and exclusive OR"gate 28, when used in conjunction with the higher order carry-out, Kproduce the lower order carry-out K Each of the AND gates 17 through 26receives a different combination of two of the five input signals. ORgate 27 has provisions to receive the 10 outputs of AND gates 17 through26. The outputs of OR gate 16 and OR gate 27 are connected to the twoinput terminals of exclusive OR gate 28. It will be remembered that theBoolean expression for an exclusive OR gate is X Y2 YZ where X is theoutput of the exclusive OR gate and Y and Z are both inputs to theexclusive OR gate. The bar over Z and l is the notation for complementof. The output of exclusive OR gate 28 is the lower order carryoutsignal, K

An example is beneficial in understanding the operation of the circuitin FIG. 2. Suppose that a b,, c and K is each a l and K, is a 0. Thenumber of input ls is four, an even number, and the output S, of paritychecker 10 is a 0. All four inputs of AND gate 15 and ls and the outputis correspondingly a 1. Therefore,

the output K of OR gate 16 is also a 1. Both inputs of AND gates 19, 21,22, 24, 25, and 26 are ls and their outputs are accordingly ls.Correspondingly, the output of OR gate 27 is at 1. This means that thetwo inputs to exclusive OR gate 28 are both ls. The output K ofexclusive OR gate, in accordance to the above equation, is a 0. It willbe seen from FIG. 1 that when only four of the five inputs are ls, thehigher order carry-out, K is a l the lower order carry-out, K is a 0,and the sum 8,, is a 0. This is the same result as was just obtained inthe example.

As another example, consider the case in which only a, is a 1. Since thenumber of input ls is odd, the sum, 8,, is a l. The output of each ANDgate 11 through 15 is a 0 because each of these AND gates produces a lat its output only when all four of the inputs to that gate are ls.Correspondingly, the output K of OR gate 16 is a 0. The output of eachAND gate 17 through 26 is a 0 because each of these AND gates produces al at its output only when both the two inputs to that gate are ls.Correspondingly, the output of OR gate 27 is a 0. Since both inputs toexclusive OR gate 28 are 0's, its output, K is also a 0 in accordancewith the exclusive OR equation given above. Looking at FIG. 1, it may beseen that when only one input 1 to the adder stage is present the sum,8,, is a l and the lower order carry-out, K and the higher ordercarryout, K are both Os.

FIG. 3 is a schematic diagram of the i" addition stage of a threecharacter adder using threshold logic. The same input and output signalsare present here as were present in FIG. 2. The threshold gates utilizedhere will produce a binary 1 at their output whenever at least thethreshold number of binary ls are among their inputs. Threshold gate 30has a threshold of four and will produce a l at its output whenever atleast four of the five inputs to it are ls. Threshold gate 30 isreceptive to all of the five input signals. The output of threshold gate30 is the higher order carry-out, K

Threshold gate 31 has a threshold of two. Threshold gate 31 is receptiveto all five of the inputs. Whenever at least two of the five inputs arels, the output of threshold gate 31 is a binary l. The outputs of boththreshold gates 30 and 31 are connected to the input terminals ofexclusive OR gate 32. The output of exclusive OR gate 32 is the lowerorder carry-out, K

Parity checker 33 is receptive to all five input signals and generates al solely when the number of input ls is odd.

Again taking the example where a,, b,, 0,, and K is each a l and K,.,,is a o, the number of input ls is four, an even number, and the outputS, of parity checker 33 is a 0. The output K of threshold gate 30 is a 1since the threshold number of this gate is four and there are four inputls present. The output of threshold gate 31 is also a 1 since thethreshold number of this gate is 2. Since the two inputs to exclusive ORgate 32 are both ls, the output, K is a 0. These results are in accordwith FIG. 1 when the number of input 1 is four.

Again taking the example where only a is a l, the number of input ls isone, an odd number, and the output S, of parity checker 33 is a 1. Sinceone is below the threshold numbers of both threshold gates 30 and 31,the outputs of both gates are 0's. Thus, the higher order carry-outsignal, K is a 0. Since the two inputs to exclusive OR gate 32 arebothOs, the output, K is a 0. These results are in accord with FIG. 1when the number of input ls is one.

Thus, circuits shown in FIG. 1 and FIG. 2 operate in accordance with thetruth table of a three character adder stage indicated by dashed line 8in FIG. 1. The sum, 8,, for an addition stage of a three character adderis a binary 1 solely whenever the number of input ls is odd. The higherorder carry-out signal, K is a binary 1 whenever the number of input lsis at least four. The lower order carry-out signal, K is the complementof the higher order carry-out signal, K whenever the number of input lsis at least two, and is the same as the higher order carry-out signalotherwise.

What is claimed is:

I. In a stage of a binary adder responsive to input signals comprisingthe operand signals for that stage and the carry-in signals fromprevious lower order stages and producing the sum for that stage and afirst carryout signal for a succeeding higher-order stage, thecombination comprising:

a pattern recognition means responsive to the input signals forproducing a control signal when the input signals conform to certainpredetermined patterns, and

means responsive to the first carry-out signal and said control signalfor producing a second carry-out signal from the first carry-out signalin accordance with said control signal.

2. The combination as recited in claim 1 wherein the second carry-outsignal producing means complements the first carry-out signal wheneversaid control signal is in a first of two states and otherwise produces asecond carry-out signal which is the same as the first carry-out signal.

3. The combination as recited in claim 2 wherein second carry-out signalproducing means includes an exclusive OR gate.

4. In a stage of a three character binary adder responsive to five inputsignals, comprising three operand signals, a lower order carrier-insignal from the next previous lower order stage, and a higher ordercarry-in signal from the second previous lower order stage; incombination means for generating the sum for that stage;

means for generating a first carry-out signal for one of the next twosucceeding higher order stages; and

means for generating a second carry-out signal comprising means forcomplementing the first carryout signal whenever the five input signalscontain at least two binary ls and otherwise making the second carry-outsignal the same as the first carryout signal.

5. The combination as recited in claim 4 wherein said means forgenerating the second carry-out signal includes:

a first logic means responsive to the five input signals for producing abinary 1 signal whenever the five input singals contain at least twobinary ls and a second logic means responsive to the output of saidfirst logic means and the first carry-out signal for generating thecomplement of the higher carry-out signal whenever the output of saidfirst logic circuit is a binary l, and otherwise making the secondcarry-out signal the same as the first carry-out signal.

6. The combination as recited in claim 5, wherein said first logic meansincludes a threshold gate having a threshold of two.

7. The combination as recited in claim 5, wherein said second logicmeans is an exclusive OR gate.

8. In a stage of a three character binary adder responsive to five inputsignals, comprising three operand signals, a lower order carry-in signalfrom the next previous lower order stage, and a higher order carry-insignal from the second previous lower order stage and generating the sumfor that stage and a higher order carry-out signal for the secondsucceeding higher order stage, the combination comprising:

a network of AND and OR gates responsive to the five input signals forproducing a binary 1 output whenever the five input signals contain atleast two binary ls, and

an exclusive OR gate responsive to the output of said network and to thehigher order carry-out signal for producing a lower order carry-outsignal for the next succeeding higher order stage.

9. In a stage of a three character binary adder responsive to five inputsignals. comprising three operand signals, a lower order carry-in signalfrom the next previous lower order stage, and a higher order carry-insignal from the second previous lower order stage, and generating thesum for that stage and a higher order carry-out for the second nexthigher order stage, the combination comprising:

a threshold gate responsive to the five input signals and having athreshold of two for producing a binary 1 output whenever the five inputsignals contain at least two binary ls, and

an exclusive OR gate responsive to the output of said threshold gate andto the higher order carry-out signal for producing a lower ordercarry-out signal to the next succeeding higher order stage.

t i t i

1. In a stage of a binary adder responsive to input signals comprisingthe operand signals for that stage and the carry-in signals fromprevious lower order stages and producing the sum for that stage and afirst carry-out signal for a succeeding higher-order stage, thecombination comprising: a pattern recognition means responsive to theinput signals for producing a control signal when the input signalsconform to certain predetermined patterns, and means responsive to thefirst carry-out signal and said control signal for producing a secondcarry-out signal from the first carry-out signal in accordance with saidcontrol signal.
 2. The combination as recited in claim 1 wherein thesecond carry-out signal producing means complements the first carry-outsignal whenever said control signal is in a first of two states andotherwise produces a second carry-out signal which is the same as thefirst carry-out signal.
 3. The combination as recited in claim 2 whereinsecond carry-out signal producing means includes an exclusive OR gate.4. In a stage of a three character binary adder responsive to five inputsignals, comprising three operand signals, a lower order carrier-insignal from the next previous lower order stage, and a higher ordercarry-in signal from the second previous lower order stage; incombination means for generating the sum for that stage; means forgenerating a first carry-out signal for one of the next two succeedinghigher order stages; and means for generating a second carry-out signalcomprising means for complementing the first carry-out signal wheneverthe five input signals contain at least two binary 1''s and otherwisemaking the second carry-out signal the same as the first carry-outsignal.
 5. The combination as recited in claim 4 wherein said means forgenerating the second carry-out signal includes: a first logic meansresponsive to the five input signals for producing a binary 1 signalwhenever the five input singals contain at least two binary 1''s and asecond logic means responsive to the output of said first logic meansand the first carry-out signal for generating the complement of thehigher carry-out signal whenever the output of said first logic circuitis a binary 1, and otherwise making the second carry-out signal the sameas the first carry-out signal.
 6. The combination as recited in claim 5,wheRein said first logic means includes a threshold gate having athreshold of two.
 7. The combination as recited in claim 5, wherein saidsecond logic means is an exclusive OR gate.
 8. In a stage of a threecharacter binary adder responsive to five input signals, comprisingthree operand signals, a lower order carry-in signal from the nextprevious lower order stage, and a higher order carry-in signal from thesecond previous lower order stage and generating the sum for that stageand a higher order carry-out signal for the second succeeding higherorder stage, the combination comprising: a network of AND and OR gatesresponsive to the five input signals for producing a binary 1 outputwhenever the five input signals contain at least two binary 1''s, and anexclusive OR gate responsive to the output of said network and to thehigher order carry-out signal for producing a lower order carry-outsignal for the next succeeding higher order stage.
 9. In a stage of athree character binary adder responsive to five input signals.comprising three operand signals, a lower order carry-in signal from thenext previous lower order stage, and a higher order carry-in signal fromthe second previous lower order stage, and generating the sum for thatstage and a higher order carry-out for the second next higher orderstage, the combination comprising: a threshold gate responsive to thefive input signals and having a threshold of two for producing a binary1 output whenever the five input signals contain at least two binary1''s, and an exclusive OR gate responsive to the output of saidthreshold gate and to the higher order carry-out signal for producing alower order carry-out signal to the next succeeding higher order stage.